Advanced wireless networks require significant hardware acceleration in order to perform functions such as beamforming and path searching. To address these data processing requirements, CDMA systems often implement these algorithms directly with a dedicated ASIC or an on-chip coprocessor unit. Although this approach offers the highest potential performance, it carries significant design risks and is very inflexible to changes in standards and algorithms.
These and other algorithms usually involve multiplication operations. Wireless processing requires complex algorithms such as path search, matrix multiplication and FIR filters. Due to the area and power requirements for acceleration hardware to implement these algorithms, hardware sharing is a consideration in designing such systems.
Accordingly, there is a need for improved multipliers and multiplication methods.